(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a composite insulator layer to fill gaps between conductive structures, without charge generation of underlying layers.
(2) Description of Prior Art
The emergence of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed device performance to be increased, as well the the fabrication costs for a specific semiconductor chip, to be decreased. However the use of sub-micron features can result in process difficulties not encountered with semiconductor devices fabricated with larger features. For example micro-miniaturization has allowed devices to be achieved in which the space, or gap, between polysilicon gate structures, of metal oxide semiconductor field effect transistor, (MOSFET), devices, is in the range of only about 0.18 um. The requirements for interlevel dielectric, (ILD), layers, overlying the polysilicon gate structures are: to fill the narrow, (0.18 um), gap between polysilicon gate structures; to provide a gettering phenomena, that will tie up, or neutralize, deleterious mobile ions; to provide, or to allow, a planar top surface to be realized; and to inherently possess a low charge level, to avoid imparting an unwanted charge on an underlying gate insulator layer.
The above criteria for the optimum ILD layer is difficult to achieve with any specific ILD layer, and so this present invention will describe a process sequence resulting in a composite ILD layer satisfying all the above criteria. An underlying layer, of the composite ILD layer, will supply the needed gap filling property, while a second ILD layer, deposited on the underlying ILD layer, will supply the gettering requirement. The inherent charge level of the gettering layer, as a result of the thickness of the underlying ILD component, is at a distance from the gate insulator layer in which the inherent charge of this layer results in little influence on the underlying gate insulator layer. Finally an overlying ILD layer is used to accept a chemical mechanical polishing, (CMP), procedure, used to provide a planar top surface of subsequent wiring levels. Prior art, such as Yao, in U.S. Pat. No. 5,716,890, describes a composite insulator layer, used to fill gaps between conductive structures, however this prior art uses a barrier layer, covering all surfaces of the conductive structures, prior to forming the composite insulator layer. The present invention, applied to polysilicon gate structures, and thin gate insulator layers, is not designed to accept a barrier layer, but is designed to place the composite insulator layer directly on the polysilicon gate structures, and in the gaps between these structures. In addition that prior art uses a dual gettering layer, resulting in unwanted, increases in process costs.
It is an object of this invention to form a composite ILD layer overlying conductive structures, as well as overlying and filling the gaps, or spaces, between conductive structures.
It is another object of this invention to use a first layer, of the composite ILD layer, that effectively fills the gaps or spaces, between conductive structures, and is comprised with a charge level at a level low enough not to influence the flatband, and threshold voltage of underlying MOSFET devices.
It is still another object of this invention to deposit a second component of the composite ILD layer, overlying the first, underlying, low charge, gap filling insulator component, with the second component of the composite ILD layer providing a gettering characteristic, used to alleviate the effects of mobile ion charge.
It is still yet another object of this invention to deposit a third component of the composite ILD layer, overlying the second component of the composite ILD layer, for purposes of providing a layer to be subjected to a chemical mechanical polishing procedures, resulting in planarization of the top surface of the composite ILD layer.
In accordance with the present invention a method of forming a composite ILD layer, on underlying MOSFET devices comprised of conductive structures, and comprised of gaps between the conductive structures, wherein the composite ILD layer provides a first layer for the needed gap filling, a second layer for mobile ion gettering, and a third layer for planarization purposes, is described. After formation of polysilicon gate structure, on an underlying gate insulator layer, and after formation of insulator spacers, on the sides of the polysilicon gate structures, and formation of source/drain regions in a region of a semiconductor substrate, not covered by the polysilicon gate structures, a composite ILD layer is deposited. The first, or underlying component of the composite ILD layer, is a high density plasma, undoped silicon glass, (HDP USG), layer, comprised with low charge, and successfully fills the gaps, or spaces, between polysilicon gate structures. A second component of the composite ILD layer is next deposited via high density plasma, or via plasma enhanced chemical vapor deposition, (PECVD), procedures, with the second component of the composite ILD layer comprised with a P2O5 component, needed to getter mobile ions. An overlying, undoped silicon glass layer, of the composite ILD layer, is next deposited, on the P2O5 doped, underlying second component, of the composite ILD layer, followed by a chemical mechanical polishing procedure, performed to the overlying, undoped silicon glass layer, resulting in a smooth top surface of the composite ILD layer.